library IEEE;
use ieee.std_logic_1164.all;
use work.micro_simple.all;

entity concurrencia is
	generic(GND			: std_logic_vector (7 downto 0) := "00000000"
		   );
	port(
		 rst, clk      : in   std_logic;
		 data,addr : out	std_logic_vector (7 downto 0);
		 rd, wr		   : out std_logic
		 );
end concurrencia;

